1. Field of the Invention
The present invention relates to a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, and in particular to an apparatus that employs a technique for speeding up a read operation executed synchronously with an output enable signal supplied from an external device.
2. Description of Related Art
Typical examples of a semiconductor memory device include a DRAM and a SRAM. As is well known, the DRAM is more affordable in price and has a larger capacity than the SRAM, but requires a refreshing operation. The SRAM does not require any refreshing operation and is easily handled, but is more expensive and has a smaller capacity than the DRAM.
A virtual static RAM (called VSRAM) is a known semiconductor memory device having the advantages of the DRAM and the SRAM. The virtual SRAM (sometimes also called PSRAM, Pseudo Static RAM) has a memory cell array of dynamic memory cells like the DRAM, and includes a refresh controller to perform the internal refreshing operation synchronously with an output enable signal or a write enable signal supplied from an external device.
One example of techniques of a refresh control for a virtual SRAM is disclosed in JP2002-74945A.
It is preferable that a speed of reading data from a semiconductor memory device is high. The same is true for a virtual SRAM.
In a conventional virtual SRAM, a refreshing operation is executed in preference to a read access operation in a read operation cycle in which the reading of data from an external device (hereinafter referred to as ‘read access’ or simply ‘access’) is performed. Accordingly, the read access operation sometimes has to wait for the refreshing operation to be completed. This results in slowing down of an access speed in the read access operation. Hereinafter the read operation cycle is sometimes referred to as ‘read cycle.’ The write operation cycle, in which writing (hereinafter referred to as ‘write access’ or simply ‘access’) is performed, is sometimes referred to as ‘write cycle.’
The present invention is made to address the above mentioned problem, and to provide apparatus and techniques which achieve speeding up of a read access in a semiconductor memory device equipped with a memory cell array, for example, in which dynamic memory cells, e.g., a virtual SRAM, are arrayed in a matrix.